1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. It is particularly related to a nonvolatile semiconductor memory characteristic of a floating gate electrode edge structure in a memory cell transistor with a two-layer gate electrode transistor structure, and a fabrication method for the same.
2. Description of the Related Art
Conventionally, a NOR flash memory and a NAND flash memory are known and widely used as nonvolatile semiconductor memories.
In recent years, a flash memory having the advantages of both a NOR flash memory and a NAND flash memory has been proposed (see Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Application”, Non-Volatile Semiconductor Memory Workshop 4.1, 1997, for example). This flash memory comprises memory cells, each including two MOS transistors. In such memory cell, one of the MOS transistors serving as a nonvolatile memory unit has a structure including a control gate and a floating gate, and is connected to a bit line. The other MOS transistor is connected to a source line, and is used for memory cell selection.
With an exemplary two-layer gate electrode transistor structure in which a floating gate electrode and a control gate electrode are stacked, isolation of the floating gate electrode is carried out through a slitting process. For example, a proposed slitting process is disclosed in Japanese Patent Application Laid-open 2002-83884.
With this two-layer gate electrode isolation process, the layer thickness of the floating gate electrode on a device isolation region is nearly the same as the vertical thickness (height) of an inter-gate insulator film. Thus, in the case of processing, under a condition such as low selectivity relative to the floating gate electrode, a sidewall insulator film is etched, and at the same time the floating gate electrode is also etched. This process makes it difficult to completely remove the inter-gate insulator film, and to prepare process margins for securing the remaining film of the floating gate electrode.
On the other hand, in order to increase the selectivity for the above processing, increased processing control such as usage of an exclusive highly selective gas chamber and prevention of etching stoppage due to a reaction product is required.
As a result, fabricating high performance cell/peripheral transistors through a simple process is difficult.